#ifndef _SATA_COMMAND_H
#define _SATA_COMMAND_H

const unsigned SOF			= 0x3737B57C;

//FIS type
const unsigned RegH2D_FIS	= 0x27;
const unsigned RegD2H_FIS	= 0x37;
const unsigned DMAact_FIS	= 0x39;
const unsigned DMAsetup_FIS = 0x41;
const unsigned Data_FIS		= 0x46;

//SATA COMMAND
const unsigned PIO_DATA_IN	= 0x20;
const unsigned PIO_DATA_OUT = 0x30;
const unsigned READ_DMA		= 0xC8;
const unsigned WRITE_DMA	= 0xCA;


/*
#define STATUS_PROGRAM_OK	0x01; // 0000_0001:SR[0] pass/fail
#define STATUS_ERASE_OK		0x01; // 0000_0001:SR[0] pass/fail
#define STATUS_BUSY			0x40; // 0100_0000:SR[6] busy/ready
#define STATUS_PROTECTED	0x80; // 1000_0000:SR[7] write protect
*/

//Transport FSM

// Device to Host FIS
const unsigned int DT_DeviceIdle	= 0;
const unsigned int DT_RegDHFIS0 	= 100;
const unsigned int DT_RegDHFIS1		= 101;
const unsigned int DT_RegDHFIS2		= 102;
const unsigned int DT_RegDHFIS3		= 103;
const unsigned int DT_RegDHFIS4		= 104;

const unsigned int DT_DMAACTFIS		= 2;
const unsigned int DT_DMASTUPDHFIS	= 3;
const unsigned int DT_DataIFIS		= 4;
const unsigned int DT_DATAItran		= 20;
const unsigned int DT_ChkTyp		= 5;

// Host to Device FIS
const unsigned int DT_RegHDFIS0		= 600;
const unsigned int DT_RegHDFIS1		= 601;
const unsigned int DT_RegHDFIS2		= 602;
const unsigned int DT_RegHDFIS3		= 603;
const unsigned int DT_RegHDFIS4		= 604;

const unsigned int DT_DataOFIS		= 7;
const unsigned int DT_DATAOREC		= 8;
//const unsigned int DT_DMASTUPDHFIS	= 9;

//Command FSM
const unsigned int Cmd_Device_idle  = 10;
const unsigned int Check_FIS		= 11;
const unsigned int Check_command	= 12;	

const unsigned int DMA_in			= 13;
const unsigned int Send_data		= 14;	
const unsigned int RD_send_status	= 15;

const unsigned int DMA_out			= 16;
const unsigned int Send_DMA_activate= 17;
const unsigned int Receive_data		= 18;
const unsigned int WR_send_status	= 19;

//ETC
const unsigned int SECTOR_SIZE		= 512;

#endif